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ASAHI KASEI
[AK4122]
AK4122
24-Bit 96kHz SRC with DIR
GENERAL DESCRIPTION The AK4122 is a digital sample rate converter (SRC) with the digital audio receiver (DIR). The input sample rate ranges from 8kHz to 96kHz. The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. By using the AK4122, the system can take very simple configuration because the AK4122 has an internal PLL and does not need any master clock at slave mode. Then the AK4122 is suitable for the application interfacing to different sample rates like Car Audio, DVD recorder, etc.
FEATURES 1. SRC * Asynchronous Sample Rate Converter * Input Sample Rate Range (fsi) : 8kHz 96kHz * Output Sample Rate (fso) : 32kHz, 44.1kHz, 48kHz, 96kHz * Input to Output Sample Rate Ratio : 0.33 to 6 * THD+N : -113dB * I/F format : MSB justified, LSB justified (16/24bit) and I2S compatible * Clock for Master mode : 256/384/512/768fs * SRC Bypass mode * Soft Mute Function 2. DIR * 4-Channel Inputs Selector & 1-Channel Through Output * AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible * Low Jitter Analog PLL * PLL Lock Range : 32kHz 96kHz * Auto detection - Non-PCM Bit Stream - DTS-CD Bit Stream - Validity Flag - Sampling Frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz) - Unlock & Parity Error - DAT Start ID * 40-bit Channel Status Buffer * Burst Preamble bit Pc, Pd Buffer for Non-PCM bit streams * Q-subcode Buffer for CD bit streams 3. 4-wire Serial P Interface 4. Power Supply * AVDD: 3.0 3.6V (typ. 3.3V) * DVDD: 3.0 3.6V (typ. 3.3V) 5. Ta = -10 70C 6. Package : 48pin LQFP
MS0267-E-03 -1-
2004/08
ASAHI KASEI
[AK4122]
Block Diagram
INT0 INT1 INT2 RX1 RX2 RX3 RX4
RX1 RX2 RX3 RX4 OPS1-0
R
FILT
TX
TX PDN
IPS1-0
DIR PORT3 De-em Filter
OSEL
SMUTE Serial Audio I/F
LRCK BICK SDTO
PORT1 BICK1 LRCK1 SDTI
BICK1 LRCK1 SDTI
Serial Audio I/F PORT2
SRC
BYPS
ISEL1-0
LRCK BICK SDTO OMCLK
PLL
BICK2 LRCK2 SDTIO MCLK2
BICK2 LRCK2 SDTIO
Serial Audio I/F Control Register
M/S2 M/S3
AVDD AVSS
DVDD DVSS
CDTO CDTI CCLK CSN
Block diagram
MS0267-E-03 -2-
2004/08
ASAHI KASEI
[AK4122]
Ordering Guide
AK4122VQ AKD4122 -10 +70C 48pin LQFP (0.5mm pitch) Evaluation Board for AK4122
Pin Layout
OMCLK
DVDD
SDTO
DVSS
CCLK
LRCK
BVSS
BICK
INT1
48 47 46 45 44 43 42 41 40 39 38 37 CDTI CDTO TST1 INT2 TST2 TST3 M/S2 M/S3 SMUTE TST4 TST5 FILT 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 SDTIO BICK2 LRCK2 MCLK2 DVDD DVSS SDTI BICK1 LRCK1 PDN AVSS R
AK4122VQ
Top View
INT0 31 30 29 28 27 26 TST11
CSN
12 25 13 14 15 16 17 18 19 20 21 22 23 24 TST10 AVDD
AVSS
TST6
TST7
TST8
TST9
RX1
RX2
RX3
MS0267-E-03 -3-
RX4
TX
2004/08
ASAHI KASEI
[AK4122]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 Pin Name CDTI CDTO TST1 INT2 TST2 TST3 M/S2 M/S3 SMUTE TST4 TST5 I/O I O O O O I I I I I I Function Control Data Input Pin Control Data Output Pin Test 1 Pin Interrupt 2 Pin Test 2 Pin Test 3 Pin This pin should be connected to DVSS. Master / Slave Mode Pin for PORT2 "H" : Master mode, "L" : Slave Mode Master / Slave Mode Pin for PORT3 "H" : Master mode, "L" : Slave Mode Soft Mute Pin "H" : Soft Mute, "L" : Normal Operation Test 4 Pin This pin should be connected to AVSS. Test 5 Pin This pin should be connected to AVSS. PLL Loop Filter Pin 4705% resistor and 2.2F50% ceramic capacitor in parallel with a 2.2nF50% ceramic capacitor should be connected to AVSS externally. Analog Ground Pin Analog Power Supply Pin, 3.0 3.6V Test 6 Pin This pin should be connected to AVSS. Receiver Input 1 Pin with Amp for 0.2Vpp (Internal Biased Pin) Test 7 Pin This pin should be connected to AVSS. Receiver Input 2 Pin with Amp for 0.2Vpp (Internal Biased Pin) Test 8 Pin This pin should be connected to AVSS. Receiver Input 3 Pin with Amp for 0.2Vpp (Internal Biased Pin) Test 9 Pin This pin should be connected to AVSS. Receiver Input 4 Pin with Amp for 0.2Vpp (Internal Biased Pin) Test 10 Pin This pin should be connected to AVSS. Test 11 Pin
12 13 14 15 16 17 18 19 20 21 22 23 24
FILT AVSS AVDD TST6 RX1 TST7 RX2 TST8 RX3 TST9 RX4 TST10 TST11
O I I I I I I I I I O
Note: All input pins except internal biased pins should not be left floating.
MS0267-E-03 -4-
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ASAHI KASEI
[AK4122]
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
R AVSS PDN LRCK1 BICK1 SDTI DVSS DVDD MCLK2 LRCK2 BICK2 SDTIO INT0 INT1 TX SDTO BICK LRCK OMCLK DVSS DVDD BVSS CSN CCLK
I I I I I I/O I/O I/O O O O O I/O I/O I I I
External Resistor Pin 12k5% resistor should be connected to AVSS externally. Analog Ground Pin Power-Down Mode Pin "H": Power up, "L": Power down reset and initializes the control register. Input Channel Clock Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin Digital Ground Pin Digital Power Supply Pin, 3.0 3.6V Master Clock Input Pin Input / Output Channel Clock Pin Audio Serial Data Clock Pin Audio Serial Data Input / Output Pin Interrupt 0 Pin Interrupt 1 Pin Transmitter Output Pin Audio Serial Data Output Pin Audio Serial Data Clock Pin Output Channel Clock Pin Master Clock Input Pin Digital Ground Pin Digital Power Supply Pin, 3.0 3.6V Substrate Ground Pin This pin should be connected to AVSS. Chip Select Pin Control Data Clock Pin
Note: All input pins except internal biased pins should not be left floating.
MS0267-E-03 -5-
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ASAHI KASEI
[AK4122]
Handling of Unused pins
The unused digital I/O pins should be processed appropriately as below. Classification PORT1 Pin Name BICK1, LRCK1, SDTI MCLK2 BICK2, LRCK2 SDTIO M/S2 OMCLK PORT3 BICK, LRCK SDTO M/S3 RX1, RX2, RX3, RX4 INT0, INT1, INT2, TX CSN, CCLK, CDTI CDTO SMUTE TST1, TST2, TST11 TST3 TST4, TST5, TST6, TST7, TST8, TST9, TST10 Setting These pins should be connected to DVSS. This pin should be connected to DVSS. These pins should be connected to DVSS in slave mode or open in master mode. This pin should be connected to DVSS. This pin should be connected to DVDD or DVSS. This pin should be connected to DVSS. These pins should be connected to DVSS in slave mode or open in master mode. This pin should be open. This pin should be connected to DVDD or DVSS. These pins should be open. These pins should be open. These pins should be connected to DVSS. This pin should be open. This pin should be connected to DVSS. These pins should be open. This pin should be connected to DVSS. These pins should be connected to AVSS.
PORT2
DIR Control PORT Other TEST
MS0267-E-03 -6-
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ASAHI KASEI
[AK4122]
ABSOLUTE MAXIMUM RATINGS
(AVSS, BVSS, DVSS=0V; Note 1) Parameter Analog Digital |BVSS - DVSS| (Note 2) Input Current, Any Pin Except Supplies Digital Input Voltage 1 (Except RX1-4 pins) Digital Input Voltage 2 (RX1-4 pins) Ambient Temperature (Power applied) Storage Temperature Power Supplies: Symbol AVDD DVDD GND IIN VIND1 VIND2 Ta Tstg min -0.3 -0.3 -0.3 -0.3 -10 -65 max 4.6 4.6 0.3 10 DVDD+0.3 AVDD+0.3 70 150 Units V V V mA V V C C
Note 1. All voltages with respect to ground. Note 2. AVSS, BVSS and DVSS must be connected to the same ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AVSS, BVSS, DVSS=0V; Note 1) Parameter Symbol min typ Power Supplies Analog AVDD 3.0 3.3 (Note 3) Digital DVDD 3.0 3.3
Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD and DVDD is not critical.
max 3.6 AVDD
Units V V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0267-E-03 -7-
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ASAHI KASEI
[AK4122]
SRC CHARACTERISTICS (Ta=25C; AVDD=DVDD=3.3V; AVSS=BVSS=DVSS=0V; data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter Symbol min typ max Units SRC Characteristics: Resolution (Note 4) 24 Bits Input Sample Rate FSI 8 96 kHz Output Sample Rate FSO 32 96 kHz THD+N (Input = 1kHz, 0dBFS, Note 5) FSO/FSI = 44.1kHz/48kHz -113 dB FSO/FSI = 48kHz/44.1kHz -113 dB FSO/FSI = 32kHz/48kHz -114 dB FSO/FSI = 96kHz/32kHz -111 dB Worst Case (FSO/FSI = 48kHz/8kHz) -103 dB Dynamic Range (Input = 1kHz, -60dBFS, Note 5) FSO/FSI = 44.1kHz/48kHz 114 dB FSO/FSI = 48kHz/44.1kHz 115 dB FSO/FSI = 32kHz/48kHz 115 dB FSO/FSI = 96kHz/32kHz 116 dB Worst Case (FSO/FSI = 32kHz/44.1kHz) 112 dB Dynamic Range (Input = 1kHz, -60dBFS, A-weighted, Note 5) FSO/FSI = 44.1kHz/48kHz 117 dB Ratio between Input and Output Sample Rate (Note 6) FSO/FSI 0.33 6 Note 4. Input data for SRC corresponds to 24bit data. When LSB 4bit data is input, the AK4122 calculates as "0" data because SRC is 20bit calculation. Therefore, SRC outputs "0" data. Note 5. Measured by ROHDE & SCHWARZ UPD04, Rejection Filter = wide, 8192point FFT. Note 6. The "0.33" is the ratio of FSO/FSI when FSI is 96kHz and FSO is 32kHz. The "6" is the ratio of FSO/FSI when FSI is 8kHz and FSO is 48kHz.
S/PDIF RECEIVER CHARACTERISTICS (Ta=25C; AVDD, DVDD=3.0 3.6V) Parameter Symbol min typ Input Resistance Zin 10 Input Voltage VTH 200 Input Sample Frequency fs 32 -
max 96
Units k mVpp kHz
MS0267-E-03 -8-
2004/08
ASAHI KASEI
[AK4122]
FILTER CHARACTERISTICS (Ta=25C; AVDD, DVDD=3.0 3.6V; DEM=OFF) Parameter Symbol min Digital Filter Passband -0.001dB 0.985 FSO/FSI 6.000 PB 0 0.905 FSO/FSI < 0.985 PB 0 0.714 FSO/FSI < 0.905 PB 0 0.656 FSO/FSI < 0.714 PB 0 0.536 FSO/FSI < 0.656 PB 0 0.492 FSO/FSI < 0.536 PB 0 0.452 FSO/FSI < 0.492 PB 0 0.333 FSO/FSI < 0.452 PB 0 Stopband 0.985 FSO/FSI 6.000 SB 0.5417FSI 0.905 FSO/FSI < 0.985 SB 0.5021FSI 0.714 FSO/FSI < 0.905 SB 0.3965FSI 0.656 FSO/FSI < 0.714 SB 0.3643FSI 0.536 FSO/FSI < 0.656 SB 0.2974FSI 0.492 FSO/FSI < 0.536 SB 0.2732FSI 0.452 FSO/FSI < 0.492 SB 0.2510FSI 0.333 FSO/FSI < 0.452 SB 0.1822FSI Passband Ripple PR Stopband Attenuation SA 96 Group Delay (Note 7) GD -
typ
max 0.4583FSI 0.4167FSI 0.3195FSI 0.2852FSI 0.2245FSI 0.2003FSI 0.1781FSI 0.1092FSI
Units kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz dB dB 1/fs
0.01 58.5 -
Note 7. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output, when LRCK for Output data corresponds with LRCK for Input.
DC CHARACTERISTICS (Ta=25C; AVDD, DVDD=3.0 3.6V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL High-Level Output Voltage (Iout=-400A) VOH DVDD-0.4 Low-Level Output Voltage (Iout=400A) VOL Input Leakage Current Iin Parameter Power Supply Current Normal operation (PDN pin = "H") (Note 8) FSI=FSO=48kHz at Slave Mode: AVDD=DVDD=3.3V FSI=FSO=96kHz at Master Mode: AVDD=DVDD=3.3V FSI=FSO=96kHz at Master Mode: AVDD=DVDD=3.6V Power down (PDN pin = "L") (Note 9) AVDD+DVDD min
typ typ
max 30%DVDD 0.4 10 max
Units V V V V A Units
15 29 10
45 100
mA mA mA A
Note 8. Typ and max values are the value of AVDD+DVDD in each power supply voltage. Power supply current of each path@Slave Mode, AVDD=DVDD=3.3V, FSI=FSO=48kHz 1. PORT1 SRC PORT3: AVDD=5mA(typ), DVDD=10mA(typ) 2. PORT2 SRC PORT3: AVDD=5mA(typ), DVDD=10mA(typ) 3. DIR SRC PORT3: AVDD=6mA(typ), DVDD=9mA(typ) Note 9. All digital input pins are held DVSS.
MS0267-E-03 -9-
2004/08
ASAHI KASEI
[AK4122]
SWITCHING CHARACTERISTICS (Ta=25C; AVDD, DVDD=3.0 3.6V; CL=20pF) Parameter Symbol min Master Clock Timing Frequency fCLK 8.192 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK for Input data (LRCK1, LRCK2) Frequency fs 8 Duty Cycle Duty 48 LRCK for Output data (LRCK, LRCK2) Frequency (Note 10) fs 32 Duty Cycle Slave Mode Duty 48 Master Mode Duty
S/PDIF Clock Recover Frequency Audio Interface Timing Input for PORT1 BICK1 Period BICK1 Pulse Width Low Pulse Width High LRCK1 Edge to BICK1 "" (Note 11) BICK1 "" to LRCK1 Edge (Note 11) SDTI Hold Time from BICK1 "" SDTI Setup Time to BICK1 "" Input for PORT2 (Slave mode) BICK2 Period BICK2 Pulse Width Low Pulse Width High LRCK2 Edge to BICK2 "" (Note 11) BICK2 "" to LRCK2 Edge (Note 11) SDTIO Hold Time from BICK2 "" SDTIO Setup Time to BICK2 "" Output for PORT2 (Slave mode) BICK2 Period BICK2 Pulse Width Low Pulse Width High LRCK2 Edge to BICK2 "" (Note 11) BICK2 "" to LRCK2 Edge (Note 11) LRCK2 to SDTIO (MSB) (Except I2S mode) BICK2 "" to SDTIO fPLL 32
typ
max 36.864
Units MHz ns ns kHz % kHz % % kHz
50
96 52 96 52 96
50 50
tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD
1/64fs 65 65 30 30 30 30 1/64fs 65 65 30 30 30 30 1/64fs 65 65 30 30 30 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 10. Min value is 8kHz at BYPASS mode. Note 11. BICK1 rising edge must not occur at the same time as LRCK1 edge. BICK2 rising edge must not occur at the same time as LRCK2 edge.
MS0267-E-03 - 10 -
2004/08
ASAHI KASEI
[AK4122]
Parameter Output for PORT3 (Slave mode) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 11) BICK "" to LRCK Edge (Note 11) LRCK to SDTO (MSB) (Except I2S mode) BICK "" to SDTO Output for PORT2 (Master mode) BICK2 Frequency BICK2 Duty BICK2 "" to LRCK2 BICK2 "" to SDTIO Output for PORT3 (Master mode) BICK Frequency BICK Duty BICK "" to LRCK BICK "" to SDTO Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" CDTO Delay CSN "" to CDTO Hi-Z Reset Timing PDN Pulse Width (Note 12)
Symbol tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD fBCK dBCK tMBLR tBSD fBCK dBCK tMBLR tBSD tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ tPD
min 1/64fs 65 65 30 30
typ
max
Units ns ns ns ns ns ns ns Hz % ns ns Hz % ns ns ns ns ns ns ns ns ns ns ns ns ns
30 30 64fs 50 -20 -20 64fs 50 -20 -20 200 80 80 40 40 150 50 50 20 30 1000 20 30
45 70 150
(Note 13)
Note 11. BICK rising edge must not occur at the same time as LRCK edge. Note 12. In case of using INT2. When INT2 is not used, the max value is not limited. Note 13. The AK4122 can be reset by bringing the PDN pin = "L".
MS0267-E-03 - 11 -
2004/08
ASAHI KASEI
[AK4122]
Timing Diagram
1/fCLK VIH MCLK VIL tCLKH 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL
Clock Timing
tCLKL
VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD
SDTO tSDS tSDH
50%DVDD
VIH SDTI VIL
Audio Interface Timing (Slave mode) Note : BICK shows BICK1 of PORT1, BICK2 of PORT2 and BICK of PORT3. LRCK shows LRCK1 of PORT1, LRCK2 of PORT2 and LRCK of PORT3. SDTI shows SDTI of PORT1 or SDTIO of PORT2 that is used as input port. SDTO shows SDTO of PORT3 or SDTIO of PORT2 that is used as output port.
MS0267-E-03 - 12 -
2004/08
ASAHI KASEI
[AK4122]
LRCK
50%DVDD
tMBLR
dBCK 50%DVDD
BICK
tBSD
SDTO tSDS tSDH
50%DVDD
VIH SDTI VIL
Audio Interface Timing (Master mode) Note : BICK shows BICK1 of PORT1, BICK2 of PORT2 and BICK of PORT3. LRCK shows LRCK1 of PORT1, LRCK2 of PORT2 and LRCK of PORT3. SDTI shows SDTI of PORT1 or SDTIO of PORT2 that is used as input port. SDTO shows SDTO of PORT3 or SDTIO of PORT2 that is used as output port.
VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 C0 tCDH VIH R/W VIL Hi-Z
CDTO
WRITE/READ Command Input Timing
MS0267-E-03 - 13 -
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ASAHI KASEI
[AK4122]
tCSW VIH CSN VIL tCSH VIH CCLK VIL
VIH CDTI D2 D1 D0 VIL Hi-Z
CDTO
WRITE Data Input Timing
VIH CSN VIL
VIH CCLK VIL
VIH CDTI A1 A0 VIL tDCD CDTO Hi-Z D7 D6 50%DVDD
READ Data Output Timing 1
MS0267-E-03 - 14 -
2004/08
ASAHI KASEI
[AK4122]
tCSW VIH CSN VIL tCSH VIH CCLK VIL
VIH CDTI VIL tCCZ Hi-Z
CDTO
D2
D1
D0
50%DVDD
READ Data Output Timing 2
tPD PDN VIL
Power Down & Reset Timing
MS0267-E-03 - 15 -
2004/08
ASAHI KASEI
[AK4122]
OPERATION OVERVIEW Internal Signal Path
The input source of the SRC can be switched between the outputs of the DIR, PORT1 or PORT2. The input source of the PORT2 and PORT3 can be switched between the outputs of the SRC or BYPASS. When PORT2 is used as input port, PORT2 cannot use as output port. The signal path should be controlled during PWN bit = "0". The Switch Names (ISEL1-0 bits etc) in Figure 1 correspond to the register bits that control the switch function. Refer to Table 1.
DIR PORT3 De-em Filter
OSEL
PORT1 Serial Audio I/F PORT2 Serial Audio I/F SRC
BYPS
ISEL1-0
Serial Audio I/F
PLL
Figure 1. Connection Input Source & Output Source
Mode 0 1 2 3 4 5 6 7 8 9
Input PORT ISEL1-0 bit 00 : PORT1 01 : PORT2 10 : DIR 00 : PORT1 01 : PORT2 10 : DIR 00 : PORT1 10 : DIR 00 : PORT1 10 : DIR
SRC / Bypass BYPS bit 0 : SRC
Output PORT OSEL bit
Path PORT1 SRC PORT3 PORT2 SRC PORT3 DIR SRC PORT3 PORT1 PORT3 PORT2 PORT3 DIR PORT3 PORT1 SRC PORT2 DIR SRC PORT2 PORT1 PORT2 DIR PORT2
0 : PORT3 (Note 1) 1 : Bypass 0 : SRC 1 : Bypass
1 : PORT2 (Note 2)
Table 1. Path Select Default is Mode 0. (Path : PORT1 SRC PORT3) After PDN pin = "L" "H", SDTIO pin of PORT2 is the input pin. The DIF1-0 bits of the PORT1 should be set a value except "10" (I2S Compatible) when the DIR is selected as an input port. Refer to Table 6 and 7 for Master/Slave mode setting.
MS0267-E-03 - 16 -
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ASAHI KASEI
[AK4122]
Note 1. In this case, PORT2 is input port. If PORT2 is unused, the digital I/O pins should be processed appropriately by Table 2. M/S2 pin L Mode Slave Unused pin Pin I/O Setting MCLK2 I This pin should be connected to DVSS. BICK2 I This pin should be connected to DVSS. LRCK2 I This pin should be connected to DVSS. SDTIO I This pin should be connected to DVSS. MCLK2 I This pin should be connected to DVSS. BICK2 O This pin should be open. LRCK2 O This pin should be open. SDTIO I This pin should be connected to DVSS. Table 2. Pin Setting for PORT2
H
Master
Note 2. In this case, PORT3 is output port. If PORT3 is unused, the digital I/O pins should be processed appropriately by Table 3. M/S3 pin L Mode Slave Unused pin Pin I/O Setting OMCLK I This pin should be connected to DVSS. BICK I This pin should be connected to DVSS. LRCK I This pin should be connected to DVSS. SDTO O This pin should be open. OMCLK I This pin should be connected to DVSS. BICK O This pin should be open. LRCK O This pin should be open. SDTO O This pin should be open. Table 3. Pin Setting for PORT3
H
Master
System Clock
PORT1 can be operated in slave mode only. PORT2 and PORT3 work in master mode and slave mode. Internal system clock is created by internal PLL using LRCK1, LRCK2 or LRCK of DIR. The MCLK is not needed when PORT2 and PORT3 are in slave mode and then please set MCLK2 pin and OMCLK pin to DVSS. However, when PORT2 and PORT3 are used in master mode, MCLK2 pin and OMCLK pin should be supplied to MCLK. The M/S2 pin and M/S3 pin select between master and slave mode. Table 4 and 5 show setting of MCLK frequency that PORT2 and PORT3 are master mode. In case of detecting the sampling frequency by MCLK when DIR is used, MCLK (MCLK2 or OMCLK) of selected output port (PORT2 or PORT3) should be input. ICKS1 0 0 1 1 ICKS0 MCLK2 32kHz fs 48kHz 48kHz < fs 96kHz 0 256fs 256fs 1 384fs 384fs 0 512fs N/A 1 768fs N/A Table 4. MCLK2 frequency select for Master mode
Default
OCKS1 0 0 1 1
OCKS0
OMCLK 32kHz fs 48kHz 48kHz < fs 96kHz 0 256fs 256fs 1 384fs 384fs 0 512fs N/A 1 768fs N/A Table 5. OMCLK frequency select for Master mode
Default
MS0267-E-03 - 17 -
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ASAHI KASEI
[AK4122]
Master Mode and Slave Mode
When PORT2 and PORT3 are used as output port, the M/S2 pin and M/S3 pin select either master or slave mode. "H" is master mode, "L" is slave mode. In master mode, MCLK should be input and the AK4122 outputs BICK and LRCK. In slave mode, BICK and LRCK are input externally and MCLK is not needed. If PORT2 is used as input port, M/S2 pin should be set "H" or "L". M/S2 pin L L H H Data I/O Mode BICK, LRCK I/O Slave, SRC Input Input Available 1 Output Not Available 0 I/O Master, SRC Output 1 I/O Master, Bypass Table 6. Master mode/Slave mode for PORT2 BYPS bit Data I/O Mode BICK, LRCK 0 Output Slave, SRC Input 1 Output Not Available 0 Output Master, SRC Output 1 Output Master, Bypass Table 7. Master mode/Slave mode for PORT3 BYPS bit 0
M/S3 pin L L H H
Audio Interface Format
The audio interface should be controlled during PWN bit = "0". When in BYPASS mode, BICK1, BICK2 and BICK are fixed to 64fs. (1) PORT1 Four kinds of data formats can be chosen with the DIF1-0 bits (Table 8). In all modes, the serial data is in MSB first, 2's compliment format. The SDTI is latched on the rising edge of BICK1. PORT1 corresponds to slave mode only. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 Input Format LRCK 0 16bit, LSB justified H/L 1 24bit, MSB justified H/L 0 24bit, I2S Compatible L/H 1 24bit, LSB justified H/L Table 8. Audio Interface Format for PORT1 BICK 32fs 48fs 48fs 48fs
Default
Note: The DIF1-0 bits of the PORT1 should be set a value except "10" (I2S Compatible) when the DIR is selected as an input port.
LRCK
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTI(i) BICK(64fs) SDTI(i)
Don't Care 15 14 13 12 10 Don't Care 15 14 13 12 210 15 14 13 0123 7 6 5 4 3 2 1 0 15 14 13 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1
SDTI-15:MSB, 0:LSB Lch Data Rch Data
Figure 2. Mode 0 Timing MS0267-E-03 - 18 2004/08
ASAHI KASEI
[AK4122]
LRCK
012 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1
BICK(64fs) SDTI(i)
23 22 43210 Don't Care 23 22 43210 Don't Care 23
23:MSB, 0:LSB Lch Data Rch Data
Figure 3. Mode 1 Timing
LRCK
0123 21 22 23 24 25 012 21 22 23 24 25 01
BICK(64fs) SDTI(i)
23 22 4 3 2 1 0 Don't Care 23 22 43210 Don't Care
23:MSB, 0:LSB Lch Data Rch Data
Figure 4. Mode 2 Timing
LRCK
012 89 24 31 0 1 2 89 24 31 0 1
BICK(64fs) SDTI(i)
Don't Care 23:MSB, 0:LSB Lch Data Rch Data 23 8 10 Don't Care 23 8 10
Figure 5. Mode 3 Timing (2) PORT2 Four kinds of data formats can be chosen with the IDIF1-0 bits (Table 9). In all modes, the serial data is in MSB first, 2's compliment format. If PORT2 is selected the output port, the SDTIO is clocked out on the falling edge of BICK2, and if PORT2 is selected the input port, the SDTIO is latched on the rising edge of BICK2. The audio interface supports both master and slave modes. In master mode, BICK2 and LRCK2 are output with the BICK2 frequency fixed to 64fs and the LRCK2 frequency fixed to 1fs. Mode 0 1 2 3 IDIF1 0 0 1 1 IDIF0 0 1 0 1 Output Format Input Format 24bit, MSB justified 16bit, LSB justified 24bit, MSB justified 24bit, MSB justified 24bit, I2S Compatible 24bit, I2S Compatible 24bit, MSB justified 24bit, LSB justified Table 9. Audio Interface Format for PORT2 LRCK H/L H/L L/H H/L BICK 32fs 48fs 48fs 48fs
Default
MS0267-E-03 - 19 -
2004/08
ASAHI KASEI
[AK4122]
LRCK
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTIO(o) SDTIO(i)
23 22 21 15 14 13 0123 15 14 13 12 11 10 9 8 23 22 21 7 6 5 4 3 2 1 0 15 14 13 17 18 19 20 31 0 1 2 3 15 14 13 12 11 10 9 8 23 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1
BICK(64fs) SDTIO(o) SDTIO(i)
23 22 21 Don't Care 76543 15 14 13 12 10 23 22 21 Don't Care 76543 15 14 13 12 210 23
SDTIO-23:MSB, 0:LSB SDTIO-15:MSB, 0:LSB Lch Data Rch Data
Figure 6. Mode 0 Timing
LRCK
012 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1
BICK(64fs) SDTIO(o) SDTIO(i)
23 22 23 22 43210 43210 23 22 Don't Care 23 22 43210 43210 23 Don't Care 23
23:MSB, 0:LSB Lch Data Rch Data
Figure 7. Mode 1 Timing
LRCK
0123 21 22 23 24 25 012 21 22 23 24 25 01
BICK(64fs) SDTIO(o) SDTIO(i)
23 22 23 22 43210 43210 23 22 Don't Care 23 22 43210 43210 Don't Care
23:MSB, 0:LSB Lch Data Rch Data
Figure 8. Mode 2 Timing
LRCK
012 89 24 31 0 1 2 89 24 31 0 1
BICK(64fs) SDTIO(o) SDTIO(i)
23 22 16 15 23 0 8 10 23 22 16 15 23 0 8 10 23
Don't Care 23:MSB, 0:LSB
Don't Care
Lch Data
Rch Data
Figure 9. Mode 3 Timing
MS0267-E-03 - 20 -
2004/08
ASAHI KASEI
[AK4122]
(3) PORT3 Two kinds of data formats can be chosen with the ODIF bit (Table 10). In both modes, the serial data is in MSB first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK. The audio interface supports both master and slave modes. In master mode, BICK and LRCK are output with the BICK frequency fixed to 64fs and the LRCK frequency fixed to 1fs. Mode 0 1 ODIF Output Format LRCK BICK 0 24bit, MSB justified H/L 48fs 1 24bit, I2S Compatible L/H 48fs Table 10. Audio Interface Format for PORT3
Default
LRCK
0123 17 18 19 20 31 0 1 2 3 17 18 19 20 31 0 1
BICK(64fs) SDTO(o)
23 22 21 76543 23 22 21 76543 23
SDTO-23:MSB, 0:LSB Lch Data Rch Data
Figure 10. Mode 0 Timing
LRCK
0123 21 22 23 24 25 012 21 22 23 24 25 01
BICK(64fs) SDTO(o)
23 22 43210 23 22 43210
23:MSB, 0:LSB Lch Data Rch Data
Figure 11. Mode 1 Timing
MS0267-E-03 - 21 -
2004/08
ASAHI KASEI
[AK4122]
Soft Mute Operation
Soft mute operation is performed in the digital domain of the SRC output. Soft mute can be controlled by SMUTE bit or SMUTE pin. The SMUTE bit and SMUTE pin are ORed between pin and register. When SMUTE bit goes "1" or SMUTE pin goes "H", the SRC output data is attenuated by - within 1024 LRCK cycles. When the SMUTE bit returned "0" and SMUTE pin goes "L" the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled before mute state after starting of the operation, the attenuation is discontinued and returned to 0dB by the same cycles. The soft mute is effective for changing the signal source.
SM U T E (1) (3)
D AT T Level Attenuation
-
GD (2) SD T IO / SD T O GD
Figure 12. Soft Mute Function (1) The output data is attenuated by - during 1024 LRCK cycles (1024/fs). (2) Digital output delay from the digital input is called the group delay (GD). (3) If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to 0dB by the same number of clock cycles.
MS0267-E-03 - 22 -
2004/08
ASAHI KASEI
[AK4122]
De-emphasis Filter Control
The AK4122 includes the digital de-emphasis filter (tc=50/15s) by IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). (1) When input port is DIR When the input port is DIR and DEAU bit = "1", the de-emphasis filter is enabled automatically by sampling frequency (FS3-0 bit) and pre-emphasis information in the channel status. DEM1-0 bits can control the de-emphasis filter when DEAU bit = "0". When the de-emphasis filter is OFF, the internal de-emphasis filter is bypassed. When PEM bit = "0", the internal de-emphasis filter is always bypassed. PEM 1 1 1 1 0 FS3 0 0 0 x FS2 0 0 0 FS1 0 1 1 FS0 0 0 1 Mode 44.1kHz 48kHz 32kHz OFF OFF
(Others) x x x Table 11. De-emphasis Auto Control (DEAU bit = "1")
PEM 1 1 1 1
DEM1 DEM0 Mode 0 0 44.1kHz 0 1 OFF Default 1 0 48kHz 1 1 32kHz Table 12. De-emphasis Manual Control (DEAU bit = "0")
(2) When input port is PORT1 or PORT2 When PORT1 or PORT2 is selected as input port, DEM1-0 bits can control the de-emphasis filter even if DEAU bit = "0" or DEAU bit = "1". In this case, the de-emphasis filter cannot enable automatically. When the de-emphasis filter is OFF, the internal de-emphasis filter is bypassed. DEM1 DEM0 Mode 0 0 44.1kHz 0 1 OFF Default 1 0 48kHz 1 1 32kHz Table 13. De-emphasis Manual Control
System Reset and Power-Down
The AK4122 has a full power-down mode for all circuits that is activated by the PDN pin, and a partial power-down mode activated by the PWN bit. The AK4122 should be reset once at power-up by bringing PDN pin = "L". PDN pin: All analog and digital circuits are placed in power-down and reset modes by bringing PDN pin = "L". All the registers are initialized and clocks are stopped. Read/Write operations to the registers are disabled. PWN bit (Address 00H; D0): Unlike the PDN pin operation described above, internal registers and mode settings are not initialized. Read/Write operations to the registers are enabled.
MS0267-E-03 - 23 -
2004/08
ASAHI KASEI
[AK4122]
System Reset
Bringing the PDN pin = "L" sets the AK4122 power-down mode and initializes the digital filter. When PDN pin = "L", the SDTO output is "L". The AK4122 should be reset once by bringing PDN pin = "L" upon power-up. The SDTO is valid from less than 100ms after the rising of PDN after clocks are supplied, and until then, outputs "L". After the rising of PDN pin, the SDTIO pin is input pin.
External clocks (input / output port) PDN
< 100msec
don't care
(stable)
don't care
(internal state)
Power-down
PLL locktime & fs detection
normal operation
Power-down
SDTO
"0" data
normal data
"0" data
Figure 13. System Reset
Sequence of changing clocks
The recommended sequence of changing clocks is shown as Figure 14. The internal reset is executed when the input or the output clocks are changed. The SDTO is placed "0" during reset. Within 100ms, the SDTO outputs normal data. When the frequency transition occurs gradually without the phase change, the output data may have large distortion for several seconds. Then, to output normal data within 100ms, a reset by PDN pin = "L" or PWN bit = "0" is recommended when clocks are changed.
External clocks state 1 (44.1kHz) (unknown) (input port or output port) PDN pin or PWN bit (internal state)
state 2 (48kHz)
< 100msec normal operation Power down PLL locktime & fs detection Note1 normal operation
SDTIO / SDTO SMUTE (Note2, recommended) Att.Level 0dB -dB
normal data
normal data 1024/fso
1024/fso
Figure 14. Sequence of changing clocks Note 1. The data on SDTO may cause click noise. If SDTI or SDTIO is "0" from GD before PDN pin goes "L", the data on SDTO keeps "0" then no unknown data is output. Note 2. SMUTE can remove the unknown data.
MS0267-E-03 - 24 -
2004/08
ASAHI KASEI
[AK4122]
96kHz Clock Recovery
The on-chip, low jitter PLL of DIR has a wide lock range of 32kHz to 96kHz and a lock time of less than 20ms. The AK4122 has a sampling frequency detect function (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz) that uses either clock comparison against the MCLK2 or OMCLK frequency or the channel status information. The PLL loses lock when the received sync interval is incorrect.
Biphase Input
Four receiver inputs (RX1-4) of DIR are available. Each input includes an amplifier for unbalance loads that can accept 200mVpp or greater signal. The IPS1-0 bits select the receiver channel (Table 14). IPS1 0 0 1 1 IPS0 Input Data 0 RX1 1 RX2 0 RX3 1 RX4 Table 14. Recovery Data Select
Default
Biphase Output
The AK4122 can output the through data from the digital receiver inputs (RX1-4) to the TX pin. The OPS1-0 bits can select the source of the output from the TX pin. TX output can be stopped by TXE bit. AK4122 does not have the TX output buffer (Line Driver), the TX pin cannot drive the 75 coaxial cable directly. OPS1 0 0 1 1 OPS0 Output Data 0 RX1 1 RX2 0 RX3 1 RX4 Table 15. Output Data Select for TX
Default
MS0267-E-03 - 25 -
2004/08
ASAHI KASEI
[AK4122]
Biphase signal input circuit
0.1uF 75 Coax 75 RX
AK4122
Figure 15. Consumer Input Circuit (Coaxial Input) Note 1: Coax input only : if a coupling level to this input from the next RX input line pattern exceeds 50mV, an incorrect operation may occur. In this case, it is possible to lower the coupling level by adding this decoupling capacitor. Note 2: Ground of the RCA connector and terminator should be connected to AVSS of the AK4122 with low impedance on PC board.
3.3V Optical Fiber 470 O/E Optical Receiver RX
AK4122
Figure 16. Consumer Input Circuit (Optical Input, Using 3.3V Optical Receiver) When using coaxial input, the input level of the RX line is small. Care must be taken to reduce, crosstalk among RX input lines by inserting a shield pattern between them.
MS0267-E-03 - 26 -
2004/08
ASAHI KASEI
[AK4122]
Sampling Frequency and Pre-emphasis Detection
The AK4122 has two methods for detecting the sampling frequency. The sampling frequency is detected by comparing the recovered clock to the MCLK2 or OMCLK frequency, and the detected frequency is reported on FS3-0 bits. XTL1-0 bits, ICKS1-0 bits and OCKS1-0 bits can select reference MCLK2 and OMCLK (Table 16). When XTL1-0 bits = "11", the sampling frequency is detected by the channel status sampling frequency information. The detected frequency is reported on FS3-0 bits. The default values of FS3-0 bits are "0001". In case of detecting the sampling frequency by MCLK when DIR is used, MCLK (MCLK2 or OMCLK) of selected output port (PORT2 or PORT3) should be input. XTL1 XTL0 MCLK2 or OMCLK MCLK Frequency ICKS1 / OCKS1 ICKS0 / OCKS0 0 0 11.2896MHz 0 1 22.5792MHz 1 0 16.9344MHz 1 1 33.8688MHz 0 0 12.288MHz 0 1 24.576MHz 1 0 18.432MHz 1 1 36.864MHz 0 0 24.576MHz 0 1 N/A 1 0 36.864MHz 1 1 N/A Use channel status Table 16. Reference MCLK Frequency Except XTL1-0 bit = "11" Register Output fs FS3 0 0 0 0 1 1 FS2 0 0 0 0 0 0 FS1 0 0 1 1 0 1 FS0 0 1 0 1 0 0 44.1kHz Reserved 48kHz 32kHz 88.2kHz 96kHz Clock comparison (Note 1) 3% 3% 3% 3% 3% Table 17. fs Information
0
0
0
1
1 1
0 1
Default
XTL1-0 bit = "11" Consumer Mode Professional Mode (Note 2) Byte3 Byte0 Byte4 Bit3,2,1,0 Bit7,6 Bit6,5,4,3 0000 01 0000 0001 (others) 0000 0010 10 0000 0011 11 0000 (1000) 00 1010 (1010) 00 0010
Note 1. At least 3% range is identified as the value in the Table 17. In case of an intermediate frequency of these two, FS3-0 bits indicate the nearer value. When the frequency is much larger than 96kHz or much smaller than 32kHz, FS3-0 bits may indicate "1100", "1110" or "0001". Note 2. In consumer mode, Byte3 Bit3-0 are copied to FS3-0. The pre-emphasis information is detected and reported on the PEM bit. This information is extracted from channel 1 by default (CS12 bit = "0"). It can be switched to channel 2 by changing the CS12 bit in the control register. Consumer mode Professional mode Byte0 Byte0 Bit3,4,5 Bit2,3,4 OFF 0X100 100 ON 0X100 100 Table 18. PEM Information
PEM bit 0 1
Pre-emphasis
MS0267-E-03 - 27 -
2004/08
ASAHI KASEI
[AK4122]
Interrupt Handling for DIR
There are nine events that cause the INT2-0 pins to go "H". 1. UNLCK: PLL unlock state detection "1" when the PLL loses lock. The AK4122 loses lock when the distance between two preambles is not correct or when those preambles are not correct. 2. PAR: Parity error or biphase coding error detection "1" when parity error or biphase coding error is detected, updated every sub-frame cycle. Non-PCM or DTS-CD Bit Stream detection The OR function of NPCM and DTSCD bits is output to the AUTO bit. Validity flag detection "1" when validity flag is detected. Updated every sub-frame cycle. Non-audio detection "1" when the "AUDN" bit in recovered channel status indicates "1". Updated every block cycle. Sampling frequency or pre-emphasis information change detection "1" when FS3-0 or PEM bit changes. Reading 07H register resets it. U bit (Q-subcode) sync flag "1" when the Q-subcode differs from old one, and stays "1" until this register is read. Updated every sync code cycle for Q-subcode. Reading 07H register resets it. Channel status sync flag "1" when received C bits differ from old ones, and stays "1" until this register is read. Updated every block cycle. Reading 07H register resets it. DAT Start ID detection When the category code shows DAT, "1" when the Start ID of DAT is detected. Reading 08H register resets it.
3. AUTO:
4. V:
5. AUDN:
6. STC:
7. QINT:
8. CINT:
9. DAT:
INT1-0 pins output an OR'ed signal based on the above nine interrupt events. When masked, the interrupt event does not affect the operation of the INT1-0 pins (the masks do not affect the registers (UNLCK, PAR, etc.) themselves). Once INT0 pin goes to "H", it maintains "H" for 1024 cycles (this value can be changed by the EFH1-0 bits) after all events not masked by mask bits are cleared. INT1 pin immediately goes to "L" when those events are cleared. INT2 pin output a state change on the above 1 5 and an OR'ed signal based on the above 6 9. It stays "H" until 07H and 08H registers are read. Mask bits are shared with INT0. UNLCK, AUTO, V and AUDN bits indicate the interrupt status events above in real time. Once PAR, STC, QINT or CINT and DAT bit goes to "1", it stays "1" until the register is read. When the AK4122 loses lock, the channel status bits are initialized. In this initial state, INT0 and INT2 outputs the OR'ed signal between UNLCK and PAR bits. INT1 outputs the OR'ed signal to AUTO, V and AUDN. INT2-0 pins are "L" when the DIR is not selected. When DIR is used as input port and the PLL loses lock (unlock state), the output data is muted automatically. When AMUTE bit = "1", SDTIO and SDTO are muted automatically when the AK4122 detects unlock, Non-Audio or Non-PCM/DTS-CD. After the interrupt events are cleared, mute is cancelled automatically. When AMUTE bit = "0", SDTIO and SDTO outputs "L" when the PLL loses lock (unlock state), and outputs data when other errors (PAR, AUTO etc.).
MS0267-E-03 - 28 -
2004/08
ASAHI KASEI
[AK4122]
(1) UNLCK, PAR, AUTO, V and AUDN bits
Interrupt (UNLCK, PAR, AUTO, V, AUDN)
INT0 pin
Hold Time (max:4096/fs)
INT1 pin
Hold Time = 0
INT2 pin
Register 07H
"0"
Hold "1"
"0"
Read 07H
BICK, LRCK (UNLCK)
Free Run fs : around 20kHz
BICK, LRCK (except UNLCK)
SDTIO / SDTO (AMUTE = "1") (UNLCK, AUTO, V, AUDN)
Mute
SDTIO / SDTO (AMUTE = "0") (UNLCK)
"L" Output
SDTIO / SDTO (AMUTE = "0") (AUTO, V, AUDN)
SDTIO / SDTO (PAR error)
Previous Data : Normal Operation
Figure 17. INT2-0 Timing (UNLCK, PAR, AUTO, V, AUDN bits)
MS0267-E-03 - 29 -
2004/08
ASAHI KASEI
[AK4122]
(2) STC, CINT and QINT bits
Interrupt (FS3-0, PEM, C-bit, Q-sub)
Interrupt (STC, CINT, QINT)
INT0 pin (1) (1)
INT1 pin
(2)
(2)
INT2 pin
Register 07H
"0"
Hold "1"
"0"
Hold "1"
"0"
Read 07H
BICK, LRCK
SDTIO / SDTO : Normal Operation
Figure 18. INT2-0 Timing (STC, CINT, QINT bits) (1) Hold Time : max. 4096/fs (2) Hold Time = 0
MS0267-E-03 - 30 -
2004/08
ASAHI KASEI
[AK4122]
(3) DAT bit
Interrupt (DAT)
INT0 pin (1) (1)
INT1 pin
(2)
(2)
INT2 pin
Register 08H
"0"
Hold "1"
"0"
Hold "1"
"0"
Read 08H
BICK, LRCK
SDTIO / SDTO : Normal Operation
Figure 19. INT2-0 Timing (DAT bit) (1) Hold Time : max. 4096/fs (2) Hold Time = 0
MS0267-E-03 - 31 -
2004/08
ASAHI KASEI
[AK4122]
PD pin ="L" to "H" Initialize Read 07H, 08H
INT0/1 pin ="H"
Yes
No
Release Muting
Mute SDTIO / SDTO
Read 07H, 08H
(Each Error Handling)
Read 07H, 08H (Resets registers) No
INT0/1 pin ="H"
Yes
Figure 20. Interrupt Handling Sequence Example 1
MS0267-E-03 - 32 -
2004/08
ASAHI KASEI
[AK4122]
PD pin ="L" to "H" Initialize Read 07H
INT1 pin ="H"
Yes
No
Read 07H and Detect QSUB= "1"
(Read Q-buffer)
QCRC = "0" Yes INT1 pin ="L" Yes New data is valid
No
New data is invalid
No
Figure 21. Interrupt Handling Sequence Example 2
MS0267-E-03 - 33 -
2004/08
ASAHI KASEI
[AK4122]
Q-subcode buffers
The DIR of the AK4122 has a Q-subcode buffer for CD application. The AK4122 takes Q-subcode into registers under the following conditions: 1) 2) 3) 4) The sync word (S0, S1) consists of at least 16 "0"s. The start bit is "1". Those 7-bits Q-W follows to the start bit. The distance between two start bits is 8-16 bits.
The QINT bit in the control register goes "1" when the new Q-subcode differs from old one, and goes "0" when QINT bit is read.
S0 S1 S2 S3 : S97 S0 S1 S2 S3 :
1 0 0 1 1 : 1 0 0 1 1 :
2 3 4 5 6 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Q2 R2 S2 T2 U2 V2 W2 Q3 R3 S3 T3 U3 V3 W3 : : : : : : : Q97 R97 S97 T97 U97 V97 W97 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Q2 R2 S2 T2 U2 V2 W2 Q3 R3 S3 T3 U3 V3 W3 : : : : : : : (*) number of "0" : min=0; max=8. Q Figure 22. Configuration of U-bit(CD)
Q9
* 0... 0... 0... 0... : 0... 0... 0... 0... 0... :
Q2
Q3 Q4 CTRL
Q5
Q6
Q7 Q8 ADRS
Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 TRACK NUMBER INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49 MINUTE SECOND FRAME Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73 ZERO ABSOLUTE MINUTE ABSOLUTE SECOND Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97 ABSOLUTE FRAME CRC G(x)=x16+x12+x5+1
Figure 23. Q-subcode
Addr Register Name 13H Q-subcode Address / Control 14H Q-subcode Track 15H Q-subcode Index 16H Q-subcode Minute 17H Q-subcode Second 18H Q-subcode Frame 19H Q-subcode Zero 1AH Q-subcode ABS Minute 1BH Q-subcode ABS Second 1CH Q-subcode ABS Frame
D7 D6 D5 D4 Q9 Q8 *** *** Q17 Q16 *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** Q81 Q80 *** *** Figure 24. Q-subcode register map
D3 *** *** *** *** *** *** *** *** *** ***
D2 *** *** *** *** *** *** *** *** *** ***
D1 Q3 Q11 *** *** *** *** *** *** *** Q75
D0 Q2 Q10 *** *** *** *** *** *** *** Q74
MS0267-E-03 - 34 -
2004/08
ASAHI KASEI
[AK4122]
Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection
The DIR of the AK4122 has a Non-PCM steam auto-detection function. When the 32-bit mode Non-PCM preamble based on Dolby "AC-3 Data Stream in IEC60958 Interface" is detected, the NPCM bit goes to "1". The 96-bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM to "1". Once the NPCM is set to "1", it will remain "1" until 4096 frames pass through the chip without an additional sync pattern being detected (Timing diagram: Figure 27 and Figure 28). When those preambles are detected, the burst preambles Pc and Pd (Pc: burst information, Pd: length code; Refer to Table 22, 23) that follow those sync codes are stored to registers. The AK4122 also has a DTS-CD bitstream auto-detection function. When AK4122 detects DTS-CD bitstream, the DTSCD bit goes to "1". If the next sync code does not occur within 4096 frames, the DTSCD bit goes to "0" until either the AK4122 detects the stream again. OR'ed value of the NPCM and DTSCD bits are output to the AUTO bit. The AK4122 detects 14bit sync word and 16bit sync word of a DTS-CD bitstream, the detection function can be set ON/OFF by DTS14 and DTS16 bit.
Serial Control Interface
The internal registers may be either written or read by the 4-wire P interface pins: CSN, CCLK, CDTI & CDTO. The data on this interface consists of Chip address (2bits, C1/0 are fixed to "00"), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low transition of CSN. For read operations, the CDTO output goes to high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. The chip address is fixed to "00". The access to the chip address except for "00" is invalid. PDN pin = "L" resets the registers to their default values. Read/Write can be access without MCLK, BICK and , LRCK.
CSN 0 CCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI Write CDTO
C1
C0
R/W
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
CDTI Read CDTO
C1
C0
R/W
A4
A3
A2
A1
A0
Hi-Z C1 - C0 : Chip Address (Fixed to "00") R/W : READ / WRITE ("1" : WRITE, "0" : READ) A4 - A0 : Register Address D7 - D0 : Control Data
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
Figure 25. Control I/F Timing
MS0267-E-03 - 35 -
2004/08
ASAHI KASEI
[AK4122]
Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH Register Name PDN & Mode Control Selector & Clock Control Audio Interface Format DIR Control INT0 Mask INT1 Mask DAT Mask & DTS Detect Receiver Status 0 Receiver Status 1 Receiver Status 2 RX Channel Status Byte 0 RX Channel Status Byte 1 RX Channel Status Byte 2 RX Channel Status Byte 3 RX Channel Status Byte 4 Burst Preamble Pc Byte 0 Burst Preamble Pc Byte 1 Burst Preamble Pd Byte 0 Burst Preamble Pd Byte 1 Q-subcode Address / Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode ABS Minute Q-subcode ABS Second Q-subcode ABS Frame D7 XTL1 BYPS 0 CS12 MULK0 MULK1 0 UNLCK DAT 0 CR7 CR15 CR23 CR31 CR39 PC7 PC15 PD7 PD15 Q9 Q17 Q25 Q33 Q41 Q49 Q57 Q65 Q73 Q81 D6 XTL0 OSEL 0 AMUTE MPAR0 MPAR1 0 PAR DTSCD 0 CR6 CR14 CR22 CR30 CR38 PC6 PC14 PD6 PD14 Q8 Q16 Q24 Q32 Q40 Q48 Q56 Q64 Q72 Q80 D5 TXE ISEL1 0 EFH1 MAUT0 MAUT1 0 AUTO NPCM 0 CR5 CR13 CR21 CR29 CR37 PC5 PC13 PD5 PD13 Q7 Q15 Q23 Q31 Q39 Q47 Q55 Q63 Q71 Q79 D4 SMUTE ISEL0 ODIF EFH0 MV0 MV1 0 V PEM 0 CR4 CR12 CR20 CR28 CR36 PC4 PC12 PD4 PD12 Q6 Q14 Q22 Q30 Q38 Q46 Q54 Q62 Q70 Q78 D3 DEAU ICKS1 IDIF1 IPS1 MAUD0 MAUD1 DTS16 AUDN FS3 0 CR3 CR11 CR19 CR27 CR35 PC3 PC11 PD3 PD11 Q5 Q13 Q21 Q29 Q37 Q45 Q53 Q61 Q69 Q77 D2 DEM1 ICKS0 IDIF0 IPS0 MSTC0 MSTC1 DTS14 STC FS2 0 CR2 CR10 CR18 CR26 CR34 PC2 PC10 PD2 PD10 Q4 Q12 Q20 Q28 Q36 Q44 Q52 Q60 Q68 Q76 D1 DEM0 OCKS1 DIF1 OPS1 MCIT0 MCIT1 MDAT1 CINT FS1 CCRC CR1 CR9 CR17 CR25 CR33 PC1 PC9 PD1 PD9 Q3 Q11 Q19 Q27 Q35 Q43 Q51 Q59 Q67 Q75 D0 PWN OCKS0 DIF0 OPS0 MQIT0 MQIT1 MDAT0 QINT FS0 QCRC CR0 CR8 CR16 CR24 CR32 PC0 PC8 PD0 PD8 Q2 Q10 Q18 Q26 Q34 Q42 Q50 Q58 Q66 Q74
PDN pin = "L" resets the registers to their default values. When PORT1 or PORT2 are selected as input port, the status registers (07H 1CH) are initialized. Note. Unused bits must contain a "0" value. Note. For addresses from 1DH 1FH, data must not be written.
MS0267-E-03 - 36 -
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ASAHI KASEI
[AK4122]
Register Definitions
Addr Register Name 00H PDN & Mode Control R/W Default D7 XTL1 R/W 1 D6 XTL0 R/W 1 D5 TXE R/W 1 D4 SMUTE R/W 0 D3 DEAU R/W 0 D2 DEM1 R/W 0 D1 DEM0 R/W 1 D0 PWN R/W 1
PWN: Power Down Control 0 : Power down 1 : Normal operation (Default) "0" powers down all sections. The contents of all register are not initialized and enabled to write to the registers. The internal registers (00H 06H) are not initialized, however, the status registers (07H 1CH) are initialized. Read/Write operations to the registers are enabled. DEM1-0: De-emphasis Control (Table 12, 13) Initial values are "01". DEAU: De-emphasis Auto Control 0 : Disable (Default) 1 : Enable When DEAU bit = "1", the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status.
SMUTE: Soft Mute Control 0 : Normal operation (Default) 1 : SDTIO and SDTO soft mute When SMUTE bit = "1", SDTO and SDTIO outputs "L". TXE: TX Output enable 0 : Disable, TX outputs "L". 1 : Enable (Default)
XTL1-0: Reference MCLK Frequency Select (Table 16) Initial values are "11".
MS0267-E-03 - 37 -
2004/08
ASAHI KASEI
[AK4122]
Addr Register Name 01H Selector & Clock Control R/W Default
D7 BYPS R/W 0
D6 OSEL R/W 0
D5 ISEL1 R/W 0
D4 ISEL0 R/W 0
D3 ICKS1 R/W 1
D2 ICKS0 R/W 0
D1 OCKS1 R/W 1
D0 OCKS0 R/W 0
OCKS1-0: OMCLK Frequency Select for Master mode (Table 5) Initial values are "10". ICKS1-0: MCLK2 Frequency Select for Master mode (Table 4) Initial values are "10". ISEL1-0: Input Port Select Initial values are "00". ISEL1 0 0 1 1 ISEL0 Input PORT Default 0 PORT1 1 PORT2 0 DIR 1 N/A Table 19. Input PORT Select
OSEL: Output Port Select Initial values are "0". OSEL Output PORT Default 0 PORT3 1 PORT2 Table 20. Output PORT Select BYPS: Select Bypass mode 0 : SRC mode (Default) 1 : Bypass mode When BYPS bit = "1", the AK4122 outputs the clocks (BICK, LRCK) and data that is input by input port without SRC.
MS0267-E-03 - 38 -
2004/08
ASAHI KASEI
[AK4122]
Addr Register Name 02H Audio Interface Format R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 RD 0
D4 ODIF R/W 0
D3 IDIF1 R/W 0
D2 IDIF0 R/W 1
D1 DIF1 R/W 0
D0 DIF0 R/W 1
DIF1-0:
Audio Interface Format for PORT1 (Table 8) Initial values are "01".
IDIF1-0: Audio Interface Format for PORT2 (Table 9) Initial values are "01". ODIF: Audio Interface Format for PORT3 (Table 10) Initial values are "0".
Addr Register Name 03H DIR Control R/W Default
D7 CS12 R/W 0
D6 AMUTE R/W 1
D5 EFH1 R/W 0
D4 EFH0 R/W 1
D3 IPS1 R/W 0
D2 IPS0 R/W 0
D1 OPS1 R/W 0
D0 OPS0 R/W 0
OPS1-0:
Output Through Data Select for TX (Table 15) Initial values are "00". Input Recovery Data Select (Table 14) Initial values are "00". Interrupt 0 pin Hold Count Select Initial values are "01". LRCK of Table 21 is DIR's LRCK, the hold time scales with 1/fs. EFH1 0 0 1 1 EFH0 Hold Count 0 512LRCK 1 1024LRCK 0 2048LRCK 1 4096LRCK Table 21. Hold count select
IPS1-0:
EFH1-0:
Default
AMUTE: Auto Mute Control 0 : Normal operation 1 : Auto Mute (Default) When AMUTE bit = "1", SDTIO and SDTO are muted automatically when the AK4122 detects unlock, Non-Audio or Non-PCM/DTS-CD. CS12: Channel Status select 0 : Channel 1 (Default) 1 : Channel 2 This bit selects that channel status is used to derive C-bit buffers, AUDN, PEM, FS3-0, Pc, Pd and CRC.
MS0267-E-03 - 39 -
2004/08
ASAHI KASEI
[AK4122]
Addr Register Name 04H INT0 Mask R/W Default
D7 MULK0 R/W 0
D6 MPAR0 R/W 0
D5 MAUT0 R/W 1
D4 MV0 R/W 1
D3 MAUD0 R/W 1
D2 MSTC0 R/W 1
D1 MCIT0 R/W 1
D0 MQIT0 R/W 1
MQIT0:
Mask enable for QINT bit 0 : Mask disable 1 : Mask enable Mask enable for CINT bit 0 : Mask disable 1 : Mask enable Mask enable for STC bit 0 : Mask disable 1 : Mask enable
MCIT0:
MSTC0:
MAUD0: Mask enable for AUDN bit 0 : Mask disable 1 : Mask enable MV0: Mask enable for V bit 0 : Mask disable 1 : Mask enable
MAUT0: Mask enable for AUTO bit 0 : Mask disable 1 : Mask enable MPAR0: Mask enable for PAR bit 0 : Mask disable 1 : Mask enable MULK0: Mask enable for UNLCK bit 0 : Mask disable 1 : Mask enable The factor which mask bit is set to "0" affects INT0 and INT2 pins operation.
MS0267-E-03 - 40 -
2004/08
ASAHI KASEI
[AK4122]
Addr Register Name 05H INT1 Mask R/W Default
D7 MULK1 R/W 1
D6 MPAR1 R/W 1
D5 MAUT1 R/W 0
D4 MV1 R/W 0
D3 MAUD1 R/W 0
D2 MSTC1 R/W 1
D1 MCIT1 R/W 1
D0 MQIT1 R/W 1
MQIT1:
Mask enable for QINT bit 0 : Mask disable 1 : Mask enable Mask enable for CINT bit 0 : Mask disable 1 : Mask enable Mask enable for STC bit 0 : Mask disable 1 : Mask enable
MCIT1:
MSTC1:
MAUD1: Mask enable for AUDN bit 0 : Mask disable 1 : Mask enable MV1: Mask enable for V bit 0 : Mask disable 1 : Mask enable
MAUT1: Mask enable for AUTO bit 0 : Mask disable 1 : Mask enable MPAR1: Mask enable for PAR bit 0 : Mask disable 1 : Mask enable MULK1: Mask enable for UNLCK bit 0 : Mask disable 1 : Mask enable The factor which mask bit is set to "0" affects INT1 pin operation.
MS0267-E-03 - 41 -
2004/08
ASAHI KASEI
[AK4122]
Addr Register Name 06H DAT Mask & DTS Detect R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 RD 0
D4 0 RD 0
D3 DTS16 R/W 1
D2 DTS14 R/W 1
D1 MDAT1 R/W 1
D0 MDAT0 R/W 1
MDAT0: Mask enable for DAT bit 0 : Mask disable 1 : Mask enable The factor which mask bit is set to "0" affects INT0 and INT2 pins operation. MDAT1: Mask enable for DAT bit 0 : Mask disable 1 : Mask enable The factor which mask bit is set to "0" affects INT1 pin operation. DTS14: DTS-CD 14bit Sync Word Detect 0 : No detect 1 : Detect (Default) DST-CD 16bit Sync Word Detect 0 : No detect 1 : Detect (Default)
DTS16:
MS0267-E-03 - 42 -
2004/08
ASAHI KASEI
[AK4122]
Addr Register Name 07H Receiver Status 0 R/W Default
D7 UNLCK RD 0
D6 PAR RD 0
D5 AUTO RD 0
D4 V RD 0
D3 AUDN RD 0
D2 STC RD 0
D1 CINT RD 0
D0 QINT RD 0
QINT: Q-subcode Buffer Interrupt 0 : No change 1 : Changed This bit goes to "1" when Q-subcode stored in register addresses 13H to 1CH is updated. CINT: Channel Status Buffer Interrupt 0 : No change 1 : Changed This bit goes to "1" when C-bit stored in register addresses 0AH to 0EH changes. STC: Sampling Frequency or Pre-emphasis Information Change Detection 0 : No detect 1 : Detect This bit goes to "1" when either the FS3-0 or PEM bit changes. Audio Bit Output 0 : Audio 1 : Non audio This bit is made by encoding channel status bits.
AUDN:
V:
Validity Bit 0 : Valid 1 : Invalid Non-PCM or DTS-CD Bit Steam Auto Detection 0 : No detect 1 : Detect This bit outputs the OR'ed value of NPCM and DTSCD bits. Parity Error or Bi-phase Error Status 0 : No error 1 : Error This bit goes to "1" if a parity error or biphase error is detected in the sub-frame.
AUTO:
PAR:
UNLCK: PLL Lock Status 0 : Lock 1 : Unlock QINT, CINT and STC bits are initialized when 07H is read.
MS0267-E-03 - 43 -
2004/08
ASAHI KASEI
[AK4122]
Addr Register Name 08H Receiver Status 1 R/W Default
D7 DAT RD 0
D6 DTSCD RD 0
D5 NPCM RD 0
D4 PEM RD 0
D3 FS3 RD 0
D2 FS2 RD 0
D1 FS1 RD 0
D0 FS0 RD 1
FS3-0: Sampling Frequency Detection (Table 17) PEM: Pre-emphasis Detect (Table 18) 0 : OFF 1 : ON This bit is made by encoding the channel status bits. Non-PCM Bit Stream Auto Detection 0 : No detect 1 : Detect
NPCM:
DTSCD: DTS-CD Bit Stream Auto Detect 0 : No detect 1 : Detect DAT: DAT Start ID Detect 0 : No detect 1 : Detect When the category code shows DAT, "1" when the Start ID of DAT is detected. Reading 08H register resets it. DAT bit is initialized when 08H is read.
Addr Register Name 09H Receiver Status 2 R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 RD 0
D4 0 RD 0
D3 0 RD 0
D2 0 RD 0
D1 CCRC RD 0
D0 QCRC RD 0
QCRC: Cyclic Redundancy Check for Q-subcode 0 : No error 1 : Error CCRC: Cyclic Redundancy Check for Channel Status 0 : No error 1 : Error This bit is enabled only in professional mode and only for the channel selected by the CS12 bit.
MS0267-E-03 - 44 -
2004/08
ASAHI KASEI
[AK4122]
Addr 0AH 0BH 0CH 0DH 0EH
Register Name RX Channel Status Byte 0 RX Channel Status Byte 1 RX Channel Status Byte 2 RX Channel Status Byte 3 RX Channel Status Byte 4 R/W Default
D7 CR7 CR15 CR23 CR31 CR39
D6 CR6 CR14 CR22 CR30 CR38
D5 CR5 CR13 CR21 CR29 CR37
D4 CR4 CR12 CR20 CR28 CR36
D3 CR3 CR11 CR19 CR27 CR35
D2 CR2 CR10 CR18 CR26 CR34
D1 CR1 CR9 CR17 CR25 CR33
D0 CR0 CR8 CR16 CR24 CR32
RD Not initialized
CR39-0:
Receiver Channel Status Byte 4-0 All 40 bits are updated at the same time every block (192 frames) cycle.
Addr 0FH 10H 11H 12H
Register Name Burst Preamble Pc Byte 0 Burst Preamble Pc Byte 1 Burst Preamble Pd Byte 0 Burst Preamble Pd Byte 1 R/W Default
D7 PC7 PC15 PD7 PD15
D6 PC6 PC14 PD6 PD14
D5 PC5 PC13 PD5 PD13
D4 PC4 PC12 PD4 PD12
D3 PC3 PC11 PD3 PD11
D2 PC2 PC10 PD2 PD10
D1 PC1 PC9 PD1 PD9
D0 PC0 PC8 PD0 PD8
RD Not initialized
PC15-0: PD15-0:
Burst Preamble Pc Byte 0 and 1 Burst Preamble Pd Byte 0 and 1
Addr 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH
Register Name Q-subcode Address / Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode ABS Minute Q-subcode ABS Second Q-subcode ABS Frame R/W Default
D7 Q9 Q17 Q25 Q33 Q41 Q49 Q57 Q65 Q73 Q81
D6 Q8 Q16 Q24 Q32 Q40 Q48 Q56 Q64 Q72 Q80
D5 Q7 Q15 Q23 Q31 Q39 Q47 Q55 Q63 Q71 Q79
D4 Q6 Q14 Q22 Q30 Q38 Q46 Q54 Q62 Q70 Q78
D3 Q5 Q13 Q21 Q29 Q37 Q45 Q53 Q61 Q69 Q77
D2 Q4 Q12 Q20 Q28 Q36 Q44 Q52 Q60 Q68 Q76
D1 Q3 Q11 Q19 Q27 Q35 Q43 Q51 Q59 Q67 Q75
D0 Q2 Q10 Q18 Q26 Q34 Q42 Q50 Q58 Q66 Q74
RD Not initialized
Q81-2: Q-subcode All 80 bits are updated at the same time every sync code cycle for Q-subcode.
MS0267-E-03 - 45 -
2004/08
ASAHI KASEI
[AK4122]
Burst Preambles in Non-PCM Bitstreams
sub-frame of IEC60958
0 preamble 34 Aux. 78 11 12 LSB 27 28 29 30 31 MSB V U C P
16 bits of bitstream
0 15
Pa Pb Pc Pd
Burst_payload
stuffing
repetition time of the burst
Figure 26. Data Structure of IEC60958 Preamble word Pa Pb Pc Pd Length of field Contents 16 bits sync word 1 16 bits sync word 2 16 bits Burst info 16 bits Length code Table 22. Burst Preamble Word Value 0xF872 0x4E1F see Table 23 numbers of bits
MS0267-E-03 - 46 -
2004/08
ASAHI KASEI Repetition time of burst in IEC60958 frames 4096 1536
[AK4122]
Bits of Pc Value 0-4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 0 0 1
Contents data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 or 3 data or MPEG-2 without extension MPEG-2 data with extension MPEG-2 AAC ADTS MPEG-2, Layer1 Low sample rate MPEG-2, Layer2 or 3 Low sample rate reserved DTS type I DTS type II DTS type III ATRAC ATRAC2/3 reserved reserved, shall be set to "0" error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors data type dependent info bit stream number, shall be set to "0" Table 23. Field of Burst Information Pc
384 1152 1152 1024 384 1152 512 1024 2048 512 1024
5, 6 7 8-12 13-15
0
MS0267-E-03 - 47 -
2004/08
ASAHI KASEI
[AK4122]
Non-PCM Bitstream Timing
(1) When Non-PCM preamble does not arrive within 4096 frames
PDN pin
Bit stream
Pa Pb Pc1 Pd1 Repetition time
Pa Pb Pc2 Pd2 >4096 frames
Pa Pb Pc3 Pd3
AUTO bit
Pc Register
"0"
Pc1
Pc2
Pc3
Pd Register
"0"
Pd1
Pd2
Pd3
Figure 27. Timing example 1
(2) When Non-PCM bitstream stops (when MULK0=0)
INT0 pin <20mS (Lock time) Bit stream Pa Pb Pc1 Pd1 Stop 2~3 Syncs (B,M or W) AUTO bit Pc Register
Pc0
Pc1
Pcn
Pd Register
Pd0
Pd1
Pdn
Figure 28. Timing example 2
MS0267-E-03 - 48 -
2004/08
ASAHI KASEI
[AK4122]
SYSTEM DESIGN
Figure 29 shows the typical system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. * PORT2, PORT3 : Slave Mode
Digital Supply 3.0 ~ 3.6V
uP & DSP
DSP3
fso
10 0.1 48 CCLK 1 CDTI 2 CDTO 3 TST1 4 INT2 5 TST2 6 TST3 7 M/S2 8 M/S3 9 SMUTE 10 TST4 11 TST5 12 FILT TST10 TST11 TST6 TST7 TST8 TST9 RX1 RX2 RX3 RX4 470 2.2n 2.2 0.1 10 Shield Shield Shield Shield Shield AVDD AVSS 13 47 CSN 14 46 BVSS 15 45 DVDD 16 44 DVSS 17 43 OMCLK 18
42 LRCK 19
41 BICK 20
40 SDTO 21
39 TX 22
38 INT1 23
37 INT0 SDTIO 36 BICK2 35 LRCK2 34 MCLK2 33 fsi
DSP2
Top View
DVDD 32 0.1 DVSS 31 SDTI 30 BICK1 29 LRCK1 28 PDN 27 AVSS 26 R 25 12k fsi Reset 10
Digital Supply 3.0 ~ 3.6V
DSP1
24
Analog Supply 3.0 ~ 3.6V
S/PDIF sources
Note: - AVSS, BVSS and DVSS of the AK4122 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All digital input pins should not be left floating. Figure 29. Typical Connection Diagram
MS0267-E-03 - 49 -
2004/08
ASAHI KASEI
[AK4122]
1. Grounding and Power Supply Decoupling
The AK4122 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS of the AK4122 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4122 as possible, with the small value ceramic capacitor being the nearest.
2. PLL Loop-Filter
The C1 (2.2F) and R1 (470) should be connected in series and attached between FILT pin and AVSS in parallel with C2 (2.2nF). Please be careful the noise onto the FILT pin.
AK4122
FILT R1 C1 AVSS
C2
Parameter Recommended value Accuracy R1 470 -5% +5% C1 2.2F -50% +50% C2 2.2nF -50% +50% Note: The accuracy includes temperature dependence. Figure 30. Loop Filter for SRC The R2 (12k) should be connected in series and attached between R pin and AVSS. Please be careful the noise onto the R pin.
AK4122
R R2
AVSS
Parameter Recommended value Accuracy R2 12k -5% +5% Note: The accuracy includes temperature dependence. Figure 31. Loop Filter for DIR
MS0267-E-03 - 50 -
2004/08
ASAHI KASEI
[AK4122]
3. Jitter Tolerance
Figure 32 shows the jitter tolerance to ILRCK for AK4122. The jitter frequency and the jitter amplitude shown in Figure 32 define the jitter quantity. When the jitter amplitude is 0.01Uipp or less, the AK4122 operate normally regardless of the jitter frequency.
AK4122 Jitter Tolerance 10.00
Amplitude [UIpp]
1.00
(3) (2)
0.10
0.01
(1)
0.00 1 10 100 Frequency [Hz] 1000 10000
(1) Normal operation (2) There is a possibility that the distortion degrades. (It may degrade up to about -50dB.) (3) There is a possibility that the output data is lost. Note: - The jitter amplitude is for ILRCK and 1UI (Unit Interval) is one cycle of ILRCK. When FSI = 48kHz, 1UI is 1/48kHz = 20.8s. Figure 32. Jitter Tolerance
MS0267-E-03 - 51 -
2004/08
ASAHI KASEI
[AK4122]
PACKAGE
48pin LQFP(Unit: mm)
9.0 0.2 7.0 36 37 25 1.40 0.05 24 9.0 0.2 1.70Max 0.13 0.13
48 1 0.22 0.08 12
13
7.0
0.16 0.07 0.5 0.10 M
0 10
0.10
0.5 0.2
Material & Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
MS0267-E-03 - 52 -
2004/08
ASAHI KASEI
[AK4122]
MARKING
AKM AK4122VQ XXXXXXX
1
XXXXXXXX: Date code identifier
MS0267-E-03 - 53 -
2004/08
ASAHI KASEI
[AK4122]
Revision History
Date (YY/MM/DD) 03/10/03 04/01/27 Revision 00 01 Reason First Edition Spec Change Page 10, 11 Contents SWITCHING CHARACTERISTICS Audio Interface Timing BICK1/BICK2/BICK Period@Slave mode: min 160ns 1/64/fs Add FILTER CHARACTERISTICS Add a sentence: "The DIF1-0 bits of the PORT1 should be set a value except "10" (I2S Compatible) when the DIR is selected as an input port." Add Jitter Tolerance
04/07/23
02
Add Spec Add Spec
9 16, 18
04/8/16
03
Add Spec
51
IMPORTANT NOTICE
* These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0267-E-03 - 54 -
2004/08

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